ESD and Latch-up

Day One:

I. ESD

A. Basic Concepts

1. Current Damage
2. Voltage Damage

B. Testing

1. Human Body Model
2. Charged Device Model
3. Machine Model

C. Input Protection Techniques

1. Examples of Failures

Lunch

2. Protection Elements
3. ESD Layers
4. Design Rules

II. Latch-up

A. Basic Parasitic Principles

1. Diodes
2. Distributed Resistance
3. SCR

a. Fundamentals of Latch-up
b. Holding Voltage
c. Trigger Current

4. Bipolar Transistors (vertical and lateral)
5. Guard Rings and Carrier Trapping
6. Metal Resistance
7. Capacitance effects
8. Floating Wells
9. Spacing Effects
10. Snap Back
11. Data Corruption (Flash, EEPROM)

Day 2:

B. Parasitic Bipolar Circuits

1.Current Mirrors
2. Latch
3. Other circuits

C. Layout Examples

1. Basic Latch-up (current injection)
2. Guard Rings
3. Rising Local Voltages

Find the Problem Exercises

Trainer : Tim Turner

Courses

Reliability Training Course:
-Data analysis and reporting

Wafer Level Reliability

Package Level Reliability

ESD and Latch-Up